1. Field of the Invention
The present invention is directed to a method and to an apparatus for adapting a clock having an arbitrary phase relation and a pulse duty factor of 1:1.+-.10% to a plesiochronous, spike-free data signal and for clocking the data signal with the adapted clock.
2. Description of the Prior Art
In larger digital communications transmission systems, it is becoming increasingly difficult to construct a suitable clock distribution system for operation in clock-controlled synchronism given higher bit rates such as 139.264 or 155.52 Mbit/s. When, however, the required clocks are locally produced by distributed clock generators having a nominally identical frequency given an accuracy greater than 10.sup.-4, then the problem arises that the incoming plesiochronous data signals must be synchronized to the local clock.
An earlier European patent application (88117055.9) is already directed to a method for the reception of a binary data signal that may also exhibit phase skips upon utilization of a clock whose frequency is plesiochronous with or identical to the bit rate of the data signal and whose phase difference compared to the data signal is arbitrary. A sequence of clocks exhibiting approximately identical phase spacings is formed from the cock via a delay line chain, short pulses being derived from these clocks. Upon arrival of each edge of the data signal selected as effective, a potentially delayed interrogation pulse is derived with which a presence of pulses is interrogated via AND gates. When such pulses are present, then clocks selected via SR flip-flops and AND gates are through connected or are employed as read-in clocks OR operated. The overall running time of these method steps may potentially be compensated by such a delay that the effective edge of the read-in clock always appears half a period after the effective edge of the data signal.